Tabla de Contenidos
66.01 Técnica Digital - Trabajo Práctico - Cardiómetro
Período: 1er Cuatrimestre 2006
Alumnos:
- Albani Francisco
- Figueroa Gonzalo
Informe
Realizado en 
.
Para la carátula y el índice se consultó: Template para hacer TP's en LaTeX, por Diego Essaya
Para las ecuaciones matemáticas y las referencias externas se consultó: Ecuaciones en LaTeX, por Sebastián Santisi
Los gráficos fueron creados con GnuPlot.
Descargar PDF: 66.01.tp.cardiometro.pdf
\documentclass{article}
\usepackage[spanish]{babel}
\usepackage[latin1]{inputenc}
\usepackage{graphicx}
\usepackage{float}
\usepackage{longtable}
\title{Cardiómetro digital}
\author{Albani Francisco\and Figueroa Gonzalo}
\begin{document}
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\Huge{66.01 Técnica Digital}\\
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\Huge{Cardiómetro}\\
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Albani Francisco \hspace{1cm}\= 84xxx\\
Figueroa Gonzalo \> 84xxx\\
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\flushright{1\sptext{er} cuatrimestre 2006}
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\tableofcontents
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\section{Introducción}
El objetivo del trabajo es interiorizar los conocimientos adquiridos durante la cursada de la materia sobre circuitos digitales mediante el diseño e implementación de un dispositivo digital que sea capaz de realizar alguna tarea útil.
El dispositivo elegido para diseñar e implementar digitalmente fue uno capaz de medir las pulsaciones por minuto de una persona a través de un micrófono e informarlas con un display numérico. La naturaleza del mismo es muy similar a la de un frecuenciómetro, con la diferencia que este estará adaptado a los rangos comunes de frecuencia cardíaca. Es por esto que lleva el nombre de Cardiómetro.
\clearpage
\section{Análisis del Modelo}
\subsection{Aspecto Matemático}
El sistema estudiado se considera como un espacio lineal en el cual tienen lugar sucesos. Cada uno de estos sucesos se identifica con un latido. Para obtener la frecuencia $ f $ con la que estos sucesos se dan, es necesario de alguna manera conocer el tiempo $ T $ que transcurre entre cada uno, también llamado período. Para medir este tiempo, se utiliza una fuente con una frecuencia fija conocida $ f_c $ que se activa a la llegada de un latido y se detiene en la llegada del próximo. Durante ese intervalo, se almacena en un contador la cantidad de eventos generados por esta fuente para luego dividirlo por la frecuencia conocida y obtener el período.
Matemáticamente:
$$ \frac{f_c}{Hz} \mbox{ -------------------- } 1 s $$
$$ n_c \mbox{ -------------------- } \frac{n_c}{f_c} $$
$$ \left[ \frac{n}{f_c} \right] = segundos $$
$$ \frac{n_c}{f_c} \mbox{ -------------------- } 1 \mbox{ latido} $$
$$ 60 s \mbox{ -------------------- } l.p.m. $$
Entonces:
$$ l.p.m. = \frac{60 f_c}{n_c} \frac{1}{Hz} $$
Donde:
\begin{itemize}
\item $ f_c $ es la frecuencia fija conocida ($ Hz $).
\item $ n_c $ es la cantidad de eventos generados por la fuente de frecuencia fija conocida entre cada latido (adimensional).
\item $ l.p.m. $ es la cantidad de latidos por minuto (adimensional).
\end{itemize}
Debido a la dificultad que supone realizar divisiones en un circuito lógico, las mismas se reemplazan por restas sucesivas según el siguiente desarrollo:
$$ \frac{x}{y} = n $$
$$ x = ny $$
$$ x - ny = 0 $$
A partir del último resultado, podemos decir que si le restamos $ y $, $ n $ veces a $ x $, llegaremos a $ 0 $. Como solamente podemos realizar la resta una cantidad entera de veces, el resultado no siempre será exacto. Esto sucederá únicamente cuando $ x $ e $ y $ sean múltiplos.
En nuestro caso particular, $ x $ e $ y $ son enteros. Cuando no sean múltiplos, el resto de la división será mayor a $ 0 $ y menor a $ y $ lo que no permitirá seguir realizando restas enteras. El error cometido por esta imposibilidad dependerá de la posición que tenga el resto entre $ 0 $ e $ (y-1) $ y a partir de lo siguiente se ve nunca será mayor a $ 1 $:
\begin{quotation}
\noindent \textit{Dada la división $ \frac{a}{b} $, se consideran a $ x $ como el cociente real, a $ n $ como el cociente entero y a $ R $ como el resto de la división entera, de tal manera que $ x = \frac{a}{b} $ y $ a = nb + R $. Si proponemos a $ n $ como una aproximación del resultado real ($ n = \frac{a - R}{b} $) podemos ver que el error absoluto $ | x - n | $ siempre será menor que $ 1 $, lo que en principio supone una muy buena aproximación. Demostración: \\
$$ \left| x - n \right| = \left| \frac{a}{b} - \frac{a - R}{b} \right| = \left| \frac{a - a + R}{b} \right| = \left| \frac{R}{b} \right| < 1 $$}
\end{quotation}
\subsection{Algoritmo}
Habiendo mostrado el aspecto matemático del modelo, se procede a continuación a describir el algoritmo del circuito:
\begin{enumerate}
\item Se almacena la cantidad de eventos $ n_c $ generados por la fuente de frecuencia $ f_c $ entre el último latido y el anterior.
\item Se toma el valor $ 60 f_c $, se le resta $ n_c $ y se incrementa en $ 1 $ el valor de $ l.p.m. $.
\item Se toma el valor resultante de la resta anterior, se le resta $ n_c $ y se incrementa en $ 1 $ el valor de $ l.p.m. $.
\item Se repite el paso anterior mientras que $ 60 f_c \geq n_c $.
\item Se detiene el algoritmo y se dispone del valor $ l.p.m. $ final.
\end{enumerate}
\clearpage
\section{Diseño}
El circuito está dividido en una parte analógica y una parte digital. La primera es la encargada de procesar los latidos provenientes del micrófono y transformarlos en pulsos digitales. La segunda toma dichos pulsos y realiza todos los cálculos necesarios para poder mostrar en un display el resultado. Además dispone de un módulo capaz de simular un pulso de entrada con el fin de realizar pruebas controladas sobre el circuito. Esto último también nos permite no depender de la parte analógica, cuya realización y entendimiento no forma parte de los objetivos de este trabajo.
\subsection{Descripción de la parte digital}
A continuación se presenta un esquema de los módulos y las relaciones entre ellos de manera de hacer más fácil la explicación posterior:
\begin{figure}[H]
\centering
\includegraphics [scale=0.45]{esquema_modulos.png}
\caption{Esquema de los módulos.}
\end{figure}
El contador conectado al clock de frecuencia $ f_c $ está en continuo funcionamiento y se reinicia cada vez que llega un pulso. Antes de esto, se guarda una copia de su valor a la memoria sincrónica $ n_c $. Como bien se ve en el gráfico, existe un retraso que asegura que el pulso llegue primero al clock de la memoria $ n_c $ y luego al reset del contador. El valor almacenado será el \textit{restando} de las restas sucesivas que tendrán lugar a continuación.
La llegada del pulso también inicializa la memoria de operación en su valor inicial $ 60 f_c $. Esta memoria, jugará el papel del minuendo de las restas sucesivas, y para cada una tendrá un valor distinto que será el resultado de la resta anterior. La actualización del valor estará determinada por el clock \textit{rápido} y será tomado de la salida del restador. Este clock, combinado con otras condiciones, también activará el contador $ l.p.m. $, almacenándose ahí la cantidad de restas efectuadas. Una de esas otras condiciones estará dada por el resultado del comparador de tal manera que cuando no se pueda hacer más la resta, se deje fijo el contador $ l.p.m. $ para luego mostrar su valor en el display.
\subsection{Descripción de la parte analógica}
\begin{figure}[H]
\centering
\includegraphics [scale=0.35]{esquema_parte_analogica.png}
\caption{Esquemático de la parte analógica.}
\end{figure}
El esquemático esta comprendido por un de filtro activo LM741, que se encarga de filtrar la señal de sonido que es recogida por el micrófono y se entrega al amplificador de audio LM836, quien se encarga de su optimización.
\begin{figure}[H]
\centering
\includegraphics [scale=1]{LM386.png}
\caption{Amplificador LM386.}
\end{figure}
Este amplificador esta diseñado para ser usado en aplicaciones cuya alimentación este dada por un voltaje bajo ($ 4V - 18V $). Su ganancia esta seteada en 20 db pero la adición de un capacitor de $ 10 \mu $F entre los pins $ 1 $ y $ 8 $ multiplica por $ 10 $ dicha ganancia. Esta cualidad es una de las responsables de la elección del amplificador.
\clearpage
\section{Implementación}
En esta sección se describe el aspecto técnico de los módulos más relevantes del esquema.
\subsection{Clock $ f_c $}
La precisión de la medida del tiempo transcurrido entre un latido y otro, depende de la frecuencia de este clock. Para que el error no sea apreciable, esta deberá ser de un orden mayor que la frecuencia del ritmo cardíaco ($ \approx 1 Hz $). Si bien trabajar con una frecuencia muy alta, supondría una gran precisión, encontraríamos una nueva imposición dada por la capacidad del contador al cual esta conectado.
La frecuencia elegida es de aproximadamente $ 14 Hz $.
Este clock, como así también todos los utilizados, esta implementado con compuertas Schmitt Trigger (código comercial 4093).
\begin{figure}[H]
\centering
\includegraphics [scale=0.4]{schmitt_trigger2.png}
\caption{\textit{Es posible obtener un oscilador a partir de un Schmitt trigger conectándolo a una red RC donde el capacitor se conecta entre una de las entradas y tierra y el resistor se conecta entre la salida y la misma entrada. La Salida será una onda cuadrada continua cuya frecuencia dependerá de los valores de R y C, y también del umbral del Schmitt Trigger.}}
\end{figure}
\subsection{Contador $ n_c $}
A la hora de determinar la capacidad necesaria de este contador, se tuvo en cuenta el rango cardíaco normal ($ 60-180 l.p.m. $) y la frecuencia $ f_c $.
$$ l.p.m. = \frac{60 f_c}{n_c} \frac{1}{Hz} $$
$$ n_c = \frac{60 f_c}{l.p.m.} \frac{1}{Hz} $$
Para $ l.p.m. = 60 $:
$$ n_c = \frac{60 f_c}{60} \frac{1}{Hz} = 14 $$
Para $ l.p.m. = 180 $:
$$ n_c = \frac{60 f_c}{180} \frac{1}{Hz} = \frac{14}{3} = 4. \widehat{6} $$
A partir de estos resultados, se concluye que con un contador binario de 4 bits, cuyo rango va desde $ 0 $ a $ 15 $, será suficiente.
\begin{figure}[H]
\centering
\includegraphics [scale=0.3]{contador_4516.png}
\caption{\textit{Contador Binario de 4 Bits 4516. Este contador consiste en 4 flip-flops D conectados de manera sincrónica.}}
\end{figure}
\subsection{Memoria $ n_c $}
Se utilizó un integrado, cuyo código comercial es 40174, de 6 flip-flops D de los cuales solo se utilizan 4, que son los necesarios para persistir el valor del contador $ n_c $ durante las restas sucesivas.
\begin{figure}[H]
\centering
\includegraphics [scale=0.3]{memoria_40174.png}
\caption{\textit{Memoria de 6 Bits 40174.}}
\end{figure}
\subsection{Delay}
Para retrasar el pulso se optó por poner dos negadores en serie. De esta manera, se obtiene un retraso de $ 180 ns $, según las especificaciones.
\begin{figure}[H]
\centering
\includegraphics [scale=0.3]{negador_4069.png}
\caption{\textit{Integrado de 6 negadores 4069.}}
\end{figure}
\subsection{Integración de los módulos anteriores}
\begin{figure}[H]
\centering
\includegraphics [scale=0.45]{modulo_Nc.png}
\caption{\textit{Esquemático donde se muestran los módulos responsables de la medición de tiempo entre pulsos.}}
\end{figure}
\subsection{Memoria de Operación}
Considerando que $ 60 f_c $ será un número de 10 bits, se utilizaron dos memorias 40174 de 6 bits cada una. Debido a que esta memoria puede ser cambiada por dos caminos distintos (restador y valor inicial), a cada uno de los bits de su entrada se le asigna la salida de una compuerta OR que permite realizar esta conjunción.
\subsection{Comparador}
Los números involucrados en las comparaciones exigían utilizar 12 bits. Se utilizaron tres chips 74LS85 de 4 bits cada uno.
\begin{figure}[H]
\centering
\includegraphics [scale=0.6]{comparador_74ls85.png}
\caption{\textit{Comparador 74LS85.}}
\end{figure}
\subsection{Restador}
En lugar de restar directamente $ n_c $, se suma su complemento a dos. Para esto, se invierte bit a bit antes de ingresarlo al sumador para obtener su complemento a uno y luego se le suma uno al carry del sumador. Nuevamente, debido a la longitud de los números en juego, se utilizan tres sumadores de 4 bits cada uno.
\begin{figure}[H]
\centering
\includegraphics [scale=0.6]{sumador_74ls83.png}
\caption{\textit{Sumador 74LS83.}}
\end{figure}
\subsection{Habilitador J-K}
El objetivo de este Flip-Flop J-K es servir de indicador de estado. Un $ 0 $ significa que el circuito esta realizando cálculos y un $ 1 $ significa que el circuito esta esperando un nuevo latido para procesar. El estado $ 1 $ se alcanza cuando el resultado de la comparación es \textit{menor}. Permanece en este estado para que el circuito sepa que tiene que ignorar los resultados del comparador y el restador que una vez finalizada la cuenta son erróneos. El estado $ 0 $ se logra solamente cuando se termina de hacer la cuenta y viene un pulso nuevo.
Para lograr este comportamiento, la entrada \textbf{J} está conectada con la salida \textit{menor} del comparador y la entrada \textbf{K} está conectada a masa.
\begin{table}[H]
\centering
\begin{small}
\begin{tabular}{|c|c|c|}
\hline
J & K & $ Q_n $ \\
\hline
$ 0 $ & $ 0 $ & $ Q_{n-1} $ \\
$ 0 $ & $ 1 $ & $ 0 $ \\
$ 1 $ & $ 0 $ & $ 1 $ \\
$ 1 $ & $ 1 $ & $ \overline{Q}_{n-1} $ \\
\hline
\end{tabular}
\end{small}
\caption{\textit{Tabla de estados reducida de un Flip-Flop J-K}}
\label{tab:}
\end{table}
\begin{figure}[H]
\centering
\includegraphics [scale=0.6]{jk_4095.png}
\caption{\textit{Flip-Flop J-K 4095.}}
\end{figure}
\subsection{Integración de los módulos aritméticos}
\begin{figure}[H]
\centering
\includegraphics [scale=0.37]{esquema_modulos_aritmeticos.png}
\caption{\textit{Esquemático donde se muestran los módulos encargados de realizar los cálculos.}}
\end{figure}
\subsection{Contador $ l.p.m. $}
Este módulo está implementado con tres contadores BCD de 4 bits cada uno. No se utilizaron contadores binarios pues la decodificación de BCD a 7-segmentos es más simple.
\begin{figure}[H]
\centering
\includegraphics [scale=0.6]{contadorBCD_4510.png}
\caption{\textit{Contador BCD 4510.}}
\end{figure}
\subsection{Display}
Se utilizaron 3 displays 7-segmentos, de cátodo común, conectados cada uno a un conversor de BCD a 7-segmentos.
\begin{figure}[H]
\centering
\includegraphics [scale=0.7]{conversor_BCD-7seg_4511.png}
\caption{\textit{Conversor BCD a 7-segmentos 4511.}}
\end{figure}
\subsection{Integración de los módulos de salida}
\begin{figure}[H]
\centering
\includegraphics [scale=0.45]{modulos_salida.png}
\caption{\textit{Esquemático donde se muestran los módulos encargados de mostrar las pulsaciones por minuto.}}
\end{figure}
\clearpage
\section{Errores e incertezas}
Una vez construido y probado el circuito, se observaron diferencias significativas entre las frecuencias de prueba simuladas y la medición final de las mismas. Por ejemplo, dada una frecuencia de entrada constante, se aprecia una medida oscilante alrededor del valor esperado. La amplitud de estas oscilaciones crece a medida que se aumenta la frecuencia de entrada. A partir de esto, se realizó un estudio de las posibles fuentes de error:
\subsection{Contador $ n_c $}
El valor que se espera que se acumule para una frecuencia de entrada $ l.p.m. $ determinada, $ n_c = \frac{60 f_c}{l.p.m.} \frac{1}{Hz}$, puede verse alterado por la imprecisión propia del contador en, por ejemplo, $ \pm 1 $. Si comparamos el valor simulado en la entrada con el obtenido luego de la cuenta, considerando el $ n_c $ erróneo mencionado anteriormente, obtenemos la siguiente expresión:
$$ Error( l.p.m. ) = \left| l.p.m. - \frac{60 f_c}{ n_c + 1 } \right| $$
$$ Error( l.p.m. ) = \left| l.p.m. - \frac{60 f_c}{ \frac{60 f_c}{l.p.m.} + 1 } \right| $$
$$ Error( l.p.m. ) = \left| l.p.m. - \frac{60 f_c \, l.p.m.}{ 60 f_c + l.p.m. } \right| $$
A continuación se ha confeccionado un gráfico de la expresión anterior para $ 5 $ valores distintos de $ f_c $:
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Como se puede apreciar en el gráfico, el error aumenta con $ l.p.m. $. Se ve también que si se elige un valor mayor para $ f_c $, el error disminuye. Es natural pensar que fraccionando el tiempo en partes cada vez más pequeñas, la precisión aumenta. En el caso límite, donde estas particiones serían infinitesimales, se tiene:
$$ \lim_{f_c \rightarrow \infty} Error(l.p.m.) = \lim_{f_c \rightarrow \infty} \left| l.p.m. - \frac{60 f_c \, l.p.m.}{ 60 f_c + l.p.m. } \right| = ... $$
$$ ... = \lim_{f_c \rightarrow \infty} \bigg| l.p.m. - \frac{f_c}{f_c} \frac{60 \, l.p.m.}{ 60 + \underbrace{\frac{l.p.m.}{f_c}}_{\rightarrow 0} } \bigg| = \lim_{f_c \rightarrow \infty} \left| l.p.m. - \frac{60 \, l.p.m.}{60} \right| = ... $$
$$ ... = \lim_{f_c \rightarrow \infty} \left| l.p.m. - l.p.m. \right| = 0 $$ \linebreak[4]
El resultado anterior permite suponer que para frecuencias muy altas el error puede considerarse despreciable.
\textbf{Es evidente también que para la frecuencia elegida (14 Hz), el error que se produce cuando nos acercamos al límite superior del ritmo cardíaco, se vuelve muy apreciable.}
\subsection{Módulos aritméticos}
Una de las suposiciones iniciales, fue que el tiempo que se tarda en hacer la cuenta es mucho menor que el tiempo entre latidos. Esto se logra sincronizando todo el módulo con un clock $ c_k $ de alta frecuencia. Por cada pulso de este clock, se efectúa una resta. Considerando que tienen que hacerse $ l.p.m. $ restas, el tiempo total viene dado por:
$$ T_{total} = \frac{l.p.m.}{c_k} $$
En el gráfico siguiente, se puede apreciar el tiempo entre latidos $ \left( \frac{60s}{l.p.m.} \right) $ y el $ T_{total} $ para la frecuencia elegida ($ 500 Hz $).
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\caption{Tiempo entre latidos y de duración de la cuenta}
\end{figure}
Como bien se observa en el gráfico, a partir de $ 173.2 \, l.p.m. $, $ T_{total} $ supera al tiempo entre latidos; superponiéndose de esta manera el procesamiento de datos con la lectura de los mismos, lo que evidentemente conlleva a una mayor incerteza.
\clearpage
\section{Conclusión}
La realización de este proyecto constituyó un primer acercamiento a las técnicas digitales. Considerando nuestros básicos conocimientos previos a esta materia, podemos afirmar que hemos colmado muchas de las inquietudes propias de estudiantes que están dando sus primeros pasos en el diseño e implementación de soluciones electrónicas.
Particularmente hablando de la construcción del circuito podemos decir que las múltiples complicaciones, producto de la transición desde lo teórico hacia lo práctico, han sido muy útiles para consolidar el perfil ingenieril necesario para sortear dificultades que requieren más ingenio e imaginación que conocimientos.
\vfill
\begin{thebibliography}{xxx}
\bibitem[wak]{wak}
Wakerly Digital Design.
\bibitem[dat]{dat}
All Datasheet. \\
\footnotesize \texttt{[http://www.alldatasheet.com/]}.
\end{thebibliography}
\end{document}
(para poder compilarlo se necesitan estas imágenes)
Fotos
